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| HCPL-3140-500E资料 | |
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HCPL-3140-500E PDF Download |
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File Size : 116 KB
Manufacturer:AVAGO Description:The read transaction shows a request packet at clock edge T0 containing an ACT command. This causes row Ra of bank Ba of the memory component to load into the sense amp array for the bank. A second request packet at clock edge T5 contains a read (RD) command. This causes the data packet Q(a1) at edge T11 to be read from column Ca1 of the sense amp array for bank Ba. A third request packet at clock edge T7 contains another RD command. This causes the data packet Q(a2) at edge T13 to also be read from column Ca2. A final request packet at clock edge T10 contains a PRE command. The spac- ings between the request packets are constrained by the follow- |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：HCPL-3140-500E 厂 家：AVAGO 封 装：SOP8 批 号：18+ 数 量：16500 说 明： HCPL-3140-500E Broadcom Limited 高速光耦合器 |
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运 费： 所在地： 新旧程度：全新原装正品 |
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| 联系人：朱先生 李小姐 |
| 电 话：0755-83679110,0755-23125986 |
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